タグ: WSR-2533DHPL

WSR-2533DHPL factoryメモ

WSR-2533DHPLにおいて、”firmware” 領域内のKernel, RootFSを格納するtrxのMagicは特定のもの(0x5C436F74 (\Cot))でなければ、メーカーファーム上でのチェックで弾かれる模様。
こうなると、initramfsでfactoryを作るしかない。通常のsquashfsでは、trxのMagicをデフォルトの 0x48445230 (HDR0) から変更した場合、OpenWrtがRootFS領域の検出に失敗してマウントできず、boot loopを引き起こすと予想されるため。
WCR-1166DSでは、これが原因でfactoryファーム投入時にboot loopが発生していると思われる。

OpenWrtのコードで関係するのは ここここ

initramfsでのfactoryファーム生成は非常に面倒な上コード量が膨大になり、かつ可読性が著しく低下する傾向にあるので、正直やりたくない。やはり、factoryファームは無しにしてinitramfsファームを用いてブートの上sysupgradeするのが手っ取り早いか。

The tail length is 48! Update len to 7078136!
decodesize 7077892...
cp: can't stat '/usr/sbin/ubi*': No such file or directory
cp: can't stat '/usr/sbin/uboot_env': No such file or directory
token=tools, line=default
token=partitions, line=Kernel
token=Kernel, line=0x0:-
sector: Kernel -> offset=[0x0], write_len=[0x6c0004]
[get_all_mtd] MTD[0]: /dev/mtd0, 0x1000000, 0x10000, ALL
[get_all_mtd] MTD[1]: /dev/mtd1, 0x30000, 0x10000, Bootloader
[get_all_mtd] MTD[2]: /dev/mtd2, 0x10000, 0x10000, Config
[get_all_mtd] MTD[3]: /dev/mtd3, 0x10000, 0x10000, Factory
[get_all_mtd] MTD[4]: /dev/mtd4, 0x7c0000, 0x10000, Kernel
[get_all_mtd] MTD[5]: /dev/mtd5, 0x53b8f0, 0x10000, RootFS
[get_all_mtd] MTD[6]: /dev/mtd6, 0x7c0000, 0x10000, Kernel2
[get_all_mtd] MTD[7]: /dev/mtd7, 0x53b8f0, 0x10000, RootFS2
[get_all_mtd] MTD[8]: /dev/mtd8, 0x10000, 0x10000, glbcfg
[get_all_mtd] MTD[9]: /dev/mtd9, 0x10000, 0x10000, board_data
[merge_sector_info] sector[0]: name=[Kernel], dev=[/dev/mtd4], offset=[0], write_len=[7077892], max_allow_size=[8126464]
[validate_file] /tmp/upload2ev4Qs: Bad trx header, magic=810697800l
[update_image] Validate CRC fail!
[WARN]: upgrade failed!
upload return: 65280
Restarting system.
広告

WSR-2533DHPL stock -> OpenWrt (Fail)

長らくメーカーファーム上でのチェックを通せずにいたが、buffalo-tagを弄ったところパスできるようになったが、その後OpenWrtでブートした際にRootFSをマウントできず止まった。

The tail length is 48! Update len to 7078136!
decodesize 7077892...
cp: can't stat '/usr/sbin/ubi*': No such file or directory
cp: can't stat '/usr/sbin/uboot_env': No such file or directory
token=tools, line=default
token=partitions, line=Kernel
token=Kernel, line=0x0:-
sector: Kernel -> offset=[0x0], write_len=[0x6c0004]
[get_all_mtd] MTD[0]: /dev/mtd0, 0x1000000, 0x10000, ALL
[get_all_mtd] MTD[1]: /dev/mtd1, 0x30000, 0x10000, Bootloader
[get_all_mtd] MTD[2]: /dev/mtd2, 0x10000, 0x10000, Config
[get_all_mtd] MTD[3]: /dev/mtd3, 0x10000, 0x10000, Factory
[get_all_mtd] MTD[4]: /dev/mtd4, 0x7c0000, 0x10000, Kernel
[get_all_mtd] MTD[5]: /dev/mtd5, 0x53b8f0, 0x10000, RootFS
[get_all_mtd] MTD[6]: /dev/mtd6, 0x7c0000, 0x10000, Kernel2
[get_all_mtd] MTD[7]: /dev/mtd7, 0x53b8f0, 0x10000, RootFS2
[get_all_mtd] MTD[8]: /dev/mtd8, 0x10000, 0x10000, glbcfg
[get_all_mtd] MTD[9]: /dev/mtd9, 0x10000, 0x10000, board_data
[merge_sector_info] sector[0]: name=[Kernel], dev=[/dev/mtd4], offset=[0], write_len=[7077892], max_allow_size=[8126464]
[validate_file] freeram=[59179008] bufferram=[3739648]
/tmp/uploadMs88aC: CRC OK
[do_default_update] filesize=[7077892], offset=[0]
[do_default_update] Erase MTD[Kernel]: start
[do_default_update] Erase MTD[Kernel]: end
[do_default_update] Write MTD[Kernel]: start
[do_default_update] Write MTD[Kernel]: end
[switch_bank] to 0, return 0
upload return: 0
MReconnect to midcore failed.
[mapi_tx_transc_req] write msg length fail Connection refused
Restarting system.

===================================================================
                MT7621   stage1 code 10:33:55 (ASIC)
                CPU=500000000 HZ BUS=166666666 HZ
==================================================================
Change MPLL source from XTAL to CR...
do MEMPLL setting..
MEMPLL Config : 0x11100000
3PLL mode + External loopback
=== XTAL-40Mhz === DDR-1200Mhz ===
PLL2 FB_DL: 0xb, 1/0 = 547/477 2D000000
PLL3 FB_DL: 0x15, 1/0 = 580/444 55000000
PLL4 FB_DL: 0x18, 1/0 = 744/280 61000000
do DDR setting..[01F40000]
Apply DDR3 Setting...(use customer AC)
          0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
      --------------------------------------------------------------------------------
0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    1
000E:|    0    0    0    0    0    0    0    0    0    1    1    1    1    1    1    1
000F:|    0    0    0    0    1    1    1    1    1    1    1    1    1    1    0    0
0010:|    1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0
0011:|    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0
0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
rank 0 coarse = 15
rank 0 fine = 72
B:|    0    0    0    0    0    0    0    0    0    0    1    1    1    0    0    0
opt_dle value:11
DRAMC_R0DELDLY[018]=00001E1F
==================================================================
                RX      DQS perbit delay software calibration 
==================================================================
1.0-15 bit dq delay value
==================================================================
bit|     0  1  2  3  4  5  6  7  8  9
--------------------------------------
0 |    13 13 15 15 11 12 13 10 9 10 
10 |    11 11 13 13 11 12 
--------------------------------------

==================================================================
2.dqs window
x=pass dqs delay value (min~max)center 
y=0-7bit DQ of every group
input delay:DQS0 =31 DQS1 = 30
==================================================================
bit     DQS0     bit      DQS1
0  (1~58)29  8  (1~56)28
1  (1~56)28  9  (1~54)27
2  (1~60)30  10  (1~59)30
3  (1~61)31  11  (1~57)29
4  (1~58)29  12  (1~58)29
5  (1~59)30  13  (1~55)28
6  (1~61)31  14  (1~60)30
7  (1~60)30  15  (1~57)29
==================================================================
3.dq delay value last
==================================================================
bit|    0  1  2  3  4  5  6  7  8   9
--------------------------------------
0 |    15 15 15 15 13 13 13 11 11 13 
10 |    11 12 14 15 11 13 
==================================================================
==================================================================
     TX  perbyte calibration 
==================================================================
DQS loop = 15, cmp_err_1 = ffff0000 
dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1 
dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2 
DQ loop=15, cmp_err_1 = ffff01ae
DQ loop=14, cmp_err_1 = ffff0180
DQ loop=13, cmp_err_1 = ffff0080
dqs_perbyte_dly.last_dqdly_pass[1]=13,  finish count=1 
DQ loop=12, cmp_err_1 = ffff0000
dqs_perbyte_dly.last_dqdly_pass[0]=12,  finish count=2 
byte:0, (DQS,DQ)=(9,8)
byte:1, (DQS,DQ)=(9,8)
20,data:99
[EMI] DRAMC calibration passed

===================================================================
                MT7621   stage1 code done 
                CPU=500000000 HZ BUS=166666666 HZ
===================================================================


U-Boot 1.1.3 (Aug  5 2016 - 17:01:25) 0.02

Board: Ralink APSoC DRAM:  128 MB
relocate_code Pointer at: 87fb8000

Config XHCI 40M PLL 
******************************
Software System Reset Occurred
******************************
flash manufacture id: ef, device id 40 18
find flash: W25Q128BV
============================================ 
Ralink UBoot Version: 5.0.0.0
-------------------------------------------- 
ASIC MT7621A DualCore (MAC to MT7530 Mode)
DRAM_CONF_FROM: Auto-Detection 
DRAM_TYPE: DDR3 
DRAM bus: 16 bit
Xtal Mode=3 OCP Ratio=1/3
Flash component: 16 MBytes NOR Flash
Date:Aug  5 2016  Time:17:01:25
============================================ 
icache: sets:256, ways:4, linesz:32 ,total:32768
dcache: sets:256, ways:4, linesz:32 ,total:32768 

 ##### The CPU freq = 880 MHZ #### 
 estimate memory size =128 Mbytes
#Reset_MT7530
set LAN/WAN WLLLL

Please choose the operation: 
   1: Load system code to SDRAM via TFTP. 
   2: Load system code then write to Flash via TFTP. 
   3: Boot system code via Flash (default).
   4: Entr boot command line interface.
   7: Load Boot Loader code then write to Flash via Serial. 
   9: Load Boot Loader code then write to Flash via TFTP.                                                                  0 
   
3: System Boot system code via Flash0.
## Booting image at bc050000 ...

=================================================
Check image validation:
Image1 Trx Check --> 
## check_trx, crc=-575298866, *crc_ret=-575298866.
OK
Image1 Header Magic Number --> OK
Image1 Header Checksum --> OK
Image1 Data Checksum --> OK

=================================================

=================================================
Check image validation:
Image2 Trx Check --> 
## check_trx, crc=-1234505007, *crc_ret=-1234505007.
OK
Image2 Header Magic Number --> OK
Image2 Header Checksum --> OK
Image2 Data Checksum --> OK

=================================================
## check Image1 return 0, check Image2 return 0, Image1 crc=-575298866, Image2 crc=-1234505007.
Image1 is ok!
Image2 is not same as Image1, copy Image1 to Image2!

Copy Image:
Image1(0x50000) to Image2(0x810000), size=0x68E000
........................................................................................................
........................................................................................................
.
.
Done!
   Image Name:   MIPS OpenWrt Linux-4.14.143
   Image Type:   MIPS Linux Kernel Image (lzma compressed)
   Data Size:    2006978 Bytes =  1.9 MB
   Load Address: 80001000
   Entry Point:  80001000
   Uncompressing Kernel Image ... OK
No initrd
## Transferring control to Linux (at address 80001000) ...
## Giving linux memsize in MB, 128

Starting kernel ...

[    0.000000] Linux version 4.14.143 (musashino205@Taiha.Net) (gcc version 7.4.0 (OpenWrt GCC 7.4.0 r0+11016-9bf7431d38)) #0 SMP Sun Sep 15 14:46:05 2019
[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
[    0.000000] MIPS: machine is Buffalo WSR-2533DHPL
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 08000000 @ 00000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] VPE topology {2,2} total 4
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000]   HighMem  empty
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000007ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0x9c/0x4d8 with crng_init=0
[    0.000000] percpu: Embedded 14 pages/cpu s26064 r8192 d23088 u57344
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 32480
[    0.000000] Kernel command line: console=ttyS0,57600 rootfstype=squashfs,jffs2
[    0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
[    0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
[    0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
[    0.000000] Writing ErrCtl register=000492b0
[    0.000000] Readback ErrCtl register=000492b0
[    0.000000] Memory: 121868K/131072K available (4789K kernel code, 246K rwdata, 1036K rodata, 1276K init, 254K bss, 9204K reserved, 0K cma-reserved, 0K highmem)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] CPU Clock: 880MHz
[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcaf478abb4, max_idle_ns: 440795247997 ns
[    0.000000] clocksource: MIPS: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 4343773742 ns
[    0.000009] sched_clock: 32 bits at 440MHz, resolution 2ns, wraps every 4880645118ns
[    0.015496] Calibrating delay loop... 586.13 BogoMIPS (lpj=2930688)
[    0.087822] pid_max: default: 32768 minimum: 301
[    0.097183] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.110205] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.126315] Hierarchical SRCU implementation.
[    0.135850] smp: Bringing up secondary CPUs ...
[    0.146319] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.146329] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.146340] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.146477] CPU1 revision is: 0001992f (MIPS 1004Kc)
[    0.205169] Synchronize counters for CPU 1: done.
[    0.276364] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.276372] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.276381] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.276458] CPU2 revision is: 0001992f (MIPS 1004Kc)
[    0.326109] Synchronize counters for CPU 2: done.
[    0.387189] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.387197] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.387205] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.387279] CPU3 revision is: 0001992f (MIPS 1004Kc)
[    0.445677] Synchronize counters for CPU 3: done.
[    0.505287] smp: Brought up 1 node, 4 CPUs
[    0.517696] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.537183] futex hash table entries: 1024 (order: 3, 32768 bytes)
[    0.549730] pinctrl core: initialized pinctrl subsystem
[    0.561419] NET: Registered protocol family 16
[    0.579962] pull PCIe RST: RALINK_RSTCTRL = 4000000
[    0.890005] release PCIe RST: RALINK_RSTCTRL = 7000000
[    0.900071] ***** Xtal 40MHz *****
[    0.906803] release PCIe RST: RALINK_RSTCTRL = 7000000
[    0.917011] Port 0 N_FTS = 1b105000
[    0.923908] Port 1 N_FTS = 1b105000
[    0.930833] Port 2 N_FTS = 1b102800
[    2.089681] PCIE2 no card, disable it(RST&CLK)
[    2.098375]  -> 21007f2
[    2.103193] PCIE0 enabled
[    2.108394] PCIE1 enabled
[    2.113573] PCI host bridge /pcie@1e140000 ranges:
[    2.123096]  MEM 0x0000000060000000..0x000000006fffffff
[    2.133463]   IO 0x000000001e160000..0x000000001e16ffff
[    2.143829] PCI coherence region base: 0xbfbf8000, mask/settings: 0x60000000
[    2.167190] mt7621_gpio 1e000600.gpio: registering 32 gpios
[    2.178509] mt7621_gpio 1e000600.gpio: registering 32 gpios
[    2.189746] mt7621_gpio 1e000600.gpio: registering 32 gpios
[    2.202416] PCI host bridge to bus 0000:00
[    2.210435] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff]
[    2.224099] pci_bus 0000:00: root bus resource [io  0xffffffff]
[    2.235844] pci_bus 0000:00: root bus resource [??? 0x00000000 flags 0x0]
[    2.249312] pci_bus 0000:00: No busn resource found for root bus, will use [bus 00-ff]
[    2.267225] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[    2.280256] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.294069] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[    2.307198] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.321029] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[    2.334502] pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
[    2.347983] pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff]
[    2.361468] pci 0000:00:01.0: BAR 1: assigned [mem 0x60210000-0x6021ffff]
[    2.374952] pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit]
[    2.389463] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.399292] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
[    2.412791] pci 0000:02:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff 64bit]
[    2.427308] pci 0000:00:01.0: PCI bridge to [bus 02]
[    2.437130] pci 0000:00:01.0:   bridge window [mem 0x60100000-0x601fffff]
[    2.452070] clocksource: Switched to clocksource GIC
[    2.463868] NET: Registered protocol family 2
[    2.473126] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[    2.486864] TCP bind hash table entries: 1024 (order: 1, 8192 bytes)
[    2.499464] TCP: Hash tables configured (established 1024 bind 1024)
[    2.512225] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    2.523722] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    2.536386] NET: Registered protocol family 1
[    2.782013] 4 CPUs re-calibrate udelay(lpj = 2924544)
[    2.793455] Crashlog allocated RAM at address 0x3f00000
[    2.804005] workingset: timestamp_bits=14 max_order=15 bucket_order=1
[    2.821011] random: fast init done
[    2.831197] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    2.842705] jffs2: version 2.2 (NAND) (SUMMARY) (LZMA) (RTIME) (CMODE_PRIORITY) (c) 2001-2006 Red Hat, Inc.
[    2.865629] io scheduler noop registered
[    2.873357] io scheduler deadline registered (default)
[    2.884372] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
[    2.898171] console [ttyS0] disabled
[    2.905238] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 19, base_baud = 3125000) is a 16550A
[    2.923164] console [ttyS0] enabled
[    2.923164] console [ttyS0] enabled
[    2.936951] bootconsole [early0] disabled
[    2.936951] bootconsole [early0] disabled
[    2.954651] MediaTek Nand driver init, version v2.1 Fix AHB virt2phys error
[    2.968911] spi-mt7621 1e000b00.spi: sys_freq: 220000000
[    2.989274] m25p80 spi0.0: w25q128 (16384 Kbytes)
[    2.998721] 7 fixed-partitions partitions found on MTD device spi0.0
[    3.011375] Creating 7 MTD partitions on "spi0.0":
[    3.020931] 0x000000000000-0x000000030000 : "u-boot"
[    3.031863] 0x000000030000-0x000000040000 : "u-boot-env"
[    3.043397] 0x000000040000-0x000000050000 : "factory"
[    3.054441] 0x000000050000-0x000000810000 : "firmware"
[    3.068725] 0x000000810000-0x000000fd0000 : "Kernel2"
[    3.079818] 0x000000fd0000-0x000000fe0000 : "glbcfg"
[    3.090684] 0x000000fe0000-0x000001000000 : "board_data"
[    3.102869] libphy: Fixed MDIO Bus: probed
[    3.174069] libphy: mdio: probed
[    4.582213] mtk_soc_eth 1e100000.ethernet: loaded mt7530 driver
[    4.594638] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 20
[    4.613452] NET: Registered protocol family 10
[    4.623865] Segment Routing with IPv6
[    4.631241] NET: Registered protocol family 17
[    4.640193] 8021q: 802.1Q VLAN Support v1.8
[    4.650825] hctosys: unable to open rtc device (rtc0)
[    4.661736] VFS: Cannot open root device "(null)" or unknown-block(0,0): error -6
[    4.676655] Please append a correct "root=" boot option; here are the available partitions:
[    4.693291] 1f00             192 mtdblock0 
[    4.693298]  (driver?)
[    4.706301] 1f01              64 mtdblock1 
[    4.706306]  (driver?)
[    4.719316] 1f02              64 mtdblock2 
[    4.719321]  (driver?)
[    4.732340] 1f03            7936 mtdblock3 
[    4.732346]  (driver?)
[    4.745348] 1f04            7936 mtdblock4 
[    4.745353]  (driver?)
[    4.758356] 1f05              64 mtdblock5 
[    4.758361]  (driver?)
[    4.771362] 1f06             128 mtdblock6 
[    4.771368]  (driver?)
[    4.784386] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[    4.802463] Rebooting in 1 seconds..

WSR-2533DHPL

とある方より、誕生日プレゼントとして頂いたもの。WSR-2533DHPからのリネームとされているものの、DHPは確認していないので全く同一なのかは不明。
DHP2と一緒にまったり弄っていくのでメモ。

Switch

未確認

MAC

  • LAN: 18:C2:BF:xx:xx:E0 (board_data, mac (text))
  • WAN: 18:C2:BF:xx:xx:E0 (board_data, mac (text))
  • 2.4G: 18:C2:BF:xx:xx:E1 (Factory, 0x4 (hex))
  • 5G: 18:C2:BF:xx:xx:E4 (Factory, 0x8004 (text))

U-Boot

  • help
    MT7621 # help
    ?       - alias for 'help'
    bootm   - boot application image from memory
    cp      - memory copy
    erase   - erase SPI FLASH memory
    go      - start application at address 'addr'
    help    - print online help
    loadb   - load binary file over serial line (kermit mode)
    md      - memory display
    mdio   - Ralink PHY register R/W command !!
    mm      - memory modify (auto-incrementing)
    nm      - memory modify (constant address)
    printenv- print environment variables
    reset   - Perform RESET of the CPU
    rf      - read/write rf register
    saveenv - save environment variables to persistent storage
    setenv  - set environment variables
    spi     - spi command
    tftpboot- boot image via network using TFTP protocol
    version - print monitor version
    

  • version
    MT7621 # version
    
    U-Boot 1.1.3 (Aug  5 2016 - 17:01:25) 0.02
    

  • printenv
    MT7621 # printenv
    bootcmd=tftp
    bootdelay=5
    baudrate=57600
    ethaddr="00:AA:BB:CC:DD:10"
    ipaddr=192.168.11.1
    serverip=192.168.11.2
    bootfile="linux.trx-recovery"
    bootpartition=0
    bootversion=0.02
    stdin=serial
    stdout=serial
    stderr=serial
    
    Environment size: 214/4092 bytes
    

Kernel

  • uname -a
    root@localhost:/# uname -a
    Linux localhost 2.6.36 #1 SMP Fri Dec 7 12:26:30 CST 2018 mips GNU/Linux
    

  • cat /proc/version
    root@localhost:/# cat /proc/version
    Linux version 2.6.36 (*******_*****@***-build-01) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #1 SMP Fri Dec 7 12:26:30 CST 2018
    

  • cat /proc/cpuinfo
    root@localhost:/# cat /proc/cpuinfo
    system type             : MT7621
    processor               : 0
    cpu model               : MIPS 1004Kc V2.15
    BogoMIPS                : 583.68
    wait instruction        : yes
    microsecond timers      : yes
    tlb_entries             : 32
    extra interrupt vector  : yes
    hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000, 0x0004, 0x0003, 0x0003]
    ASEs implemented        : mips16 dsp mt
    shadow register sets    : 1
    core                    : 0
    VCED exceptions         : not available
    VCEI exceptions         : not available
    
    processor               : 1
    cpu model               : MIPS 1004Kc V2.15
    BogoMIPS                : 583.68
    wait instruction        : yes
    microsecond timers      : yes
    tlb_entries             : 32
    extra interrupt vector  : yes
    hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000, 0x0000, 0x0000, 0x0003]
    ASEs implemented        : mips16 dsp mt
    shadow register sets    : 1
    core                    : 0
    VCED exceptions         : not available
    VCEI exceptions         : not available
    
    processor               : 2
    cpu model               : MIPS 1004Kc V2.15
    BogoMIPS                : 583.68
    wait instruction        : yes
    microsecond timers      : yes
    tlb_entries             : 32
    extra interrupt vector  : yes
    hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000, 0x0000, 0x0000, 0x0000]
    ASEs implemented        : mips16 dsp mt
    shadow register sets    : 1
    core                    : 1
    VCED exceptions         : not available
    VCEI exceptions         : not available
    
    processor               : 3
    cpu model               : MIPS 1004Kc V2.15
    BogoMIPS                : 583.68
    wait instruction        : yes
    microsecond timers      : yes
    tlb_entries             : 32
    extra interrupt vector  : yes
    hardware watchpoint     : yes, count: 4, address/irw mask: [0x0000, 0x0000, 0x0ffb, 0x0ffb]
    ASEs implemented        : mips16 dsp mt
    shadow register sets    : 1
    core                    : 1
    VCED exceptions         : not available
    VCEI exceptions         : not available
    

  • cat /proc/meminfo
    root@localhost:/# cat /proc/meminfo 
    MemTotal:         122624 kB
    MemFree:           62796 kB
    Buffers:            3636 kB
    Cached:            11320 kB
    SwapCached:            0 kB
    Active:            12084 kB
    Inactive:           9920 kB
    Active(anon):       7268 kB
    Inactive(anon):      480 kB
    Active(file):       4816 kB
    Inactive(file):     9440 kB
    Unevictable:           0 kB
    Mlocked:               0 kB
    SwapTotal:             0 kB
    SwapFree:              0 kB
    Dirty:                 0 kB
    Writeback:             0 kB
    AnonPages:          7048 kB
    Mapped:             3816 kB
    Shmem:               700 kB
    Slab:              26816 kB
    SReclaimable:       2980 kB
    SUnreclaim:        23836 kB
    KernelStack:         896 kB
    PageTables:          732 kB
    NFS_Unstable:          0 kB
    Bounce:                0 kB
    WritebackTmp:          0 kB
    CommitLimit:       61312 kB
    Committed_AS:      16496 kB
    VmallocTotal:    1048372 kB
    VmallocUsed:        9736 kB
    VmallocChunk:    1037932 kB
    

  • cat /proc/mtd
    root@localhost:/# cat /proc/mtd
    dev:    size   erasesize  name
    mtd0: 01000000 00010000 "ALL"
    mtd1: 00030000 00010000 "Bootloader"
    mtd2: 00010000 00010000 "Config"
    mtd3: 00010000 00010000 "Factory"
    mtd4: 007c0000 00010000 "Kernel"
    mtd5: 0053b8f0 00010000 "RootFS"
    mtd6: 007c0000 00010000 "Kernel2"
    mtd7: 0053b8f0 00010000 "RootFS2"
    mtd8: 00010000 00010000 "glbcfg"
    mtd9: 00010000 00010000 "board_data"
    

  • switch –help
    swconfigコマンドは存在せず。

    root@localhost:/# switch --help
    Usage:
     switch acl etype add [ethtype] [portmap]              - drop etherytype packets
     switch acl dip add [dip] [portmap]                    - drop dip packets
     switch acl dip meter [dip] [portmap][meter:kbps]      - rate limit dip packets
     switch acl dip trtcm [dip] [portmap][CIR:kbps][CBS][PIR][PBS] - TrTCM dip packets
     switch acl port add [sport] [portmap]           - drop src port packets
     switch acl L4 add [2byes] [portmap]             - drop L4 packets with 2bytes payload
     switch add [mac] [portmap]                  - add an entry to switch table
     switch add [mac] [portmap] [vlan id]        - add an entry to switch table
     switch add [mac] [portmap] [vlan id] [age]  - add an entry to switch table
     switch clear                                - clear switch table
     switch del [mac]                            - delete an entry from switch table
     switch del [mac] [fid]                  - delete an entry from switch table
     switch dip add [dip] [portmap]                  - add a dip entry to switch table
     switch dip del [dip]                        - del a dip entry to switch table
     switch dip dump                                 - dump switch dip table
     switch dip clear                                - clear switch dip table
     switch dump            - dump switch table
     switch ingress-rate on [port] [Kbps]        - set ingress rate limit on port 0~4 
     switch egress-rate on [port] [Kbps]         - set egress rate limit on port 0~4 
     switch ingress-rate off [port]              - del ingress rate limit on port 0~4 
     switch egress-rate off [port]               - del egress rate limit on port 0~4
     switch filt [mac]                           - add a SA filtering entry (with portmap 1111111) to switch table
     switch filt [mac] [portmap]                 - add a SA filtering entry to switch table
     switch filt [mac] [portmap] [vlan id]       - add a SA filtering entry to switch table
     switch filt [mac] [portmap] [vlan id] [age] - add a SA filtering entry to switch table
     switch igmpsnoop on [Query Interval] [default router portmap] - turn on IGMP snoop and  router port learning (Query Interval 1~255)
     switch igmpsnoop off                                  - turn off IGMP snoop and router port learning
     switch igmpsnoop enable [port#]                       - enable IGMP HW leave/join/Squery/Gquery
     switch igmpsnoop disable [port#]                      - disable IGMP HW leave/join/Squery/Gquery
     switch mymac [mac] [portmap]                  - add a mymac entry to switch table
     switch mirror monitor [portnumber]            - enable port mirror and indicate monitor port number
     switch mirror target [portnumber] [0:off, 1:rx, 2:tx, 3:all]  - set port mirror target
     switch phy [phy_addr]                   - dump phy register of specific port
     switch phy mt7530                       - dump mt7530 phy registers
     switch phy                                      - dump all phy registers
     switch pvid [port] [pvid]                - set pvid on port 0~4 
     switch reg r [offset]                       - register read from offset
     switch reg w [offset] [value]               - register write value to offset
     switch reg d [offset]                       - register dump
     switch sip add [sip] [dip] [portmap]            - add a sip entry to switch table
     switch sip del [sip] [dip]                          - del a sip entry to switch table
     switch sip dump                                 - dump switch sip table
     switch sip clear                                - clear switch sip table
     switch tag on [port]                        - keep vlan tag for egress packet on prot 0~4
     switch tag off [port]                       - remove vlan tag for egress packet on port 0~4
     switch vlan dump                            - dump switch table
     switch vlan set [vlan idx (NULL)][vid] [portmap]  - set vlan id and associated member
    

  • switch vlan dump
    (router mode)

    root@localhost:/# switch vlan dump
      vid  fid  portmap    s-tag
        1    0  -1111-11       0
        2    0  1----1--       0
        3    0  invalid
        4    0  invalid
        5    0  invalid
        6    0  invalid
        7    0  invalid
        8    0  invalid
        9    0  invalid
       10    0  invalid
       11    0  invalid
       12    0  invalid
       13    0  invalid
       14    0  invalid
       15    0  invalid
       16    0  invalid
    

  • cat /etc/gpio/button_map.txt
    root@localhost:/# cat /etc/gpio/button_map.txt 
    #button should be define link this
    #name=gpio
    #active=[low/high]
    #spec=duration
    #the order of the keywords are critical
    
    #define the button "wps"
    wps_sgl=6
    active=low
    spec=1000
    
    #define the button "default"
    default_sgl=3
    active=low
    spec=3000
    
    #define the button power
    poweroff_sgl=18
    active=high
    spec=300
    
    #define the switch "auto mode"
    automode=7
    active=low
    spec=0
    
    #define 1st pin of swtich "ap mode"
    apmode_sw0=12
    cowork=10
    spec=0
    
    #define 2nd pin of switch "ap mode"
    apmode_sw1=10
    cowork=12
    spec=0
    
  • bootlog
    ===================================================================
                    MT7621   stage1 code 10:33:55 (ASIC)
                    CPU=500000000 HZ BUS=166666666 HZ
    ==================================================================
    Change MPLL source from XTAL to CR...
    do MEMPLL setting..
    MEMPLL Config : 0x11100000
    3PLL mode + External loopback
    === XTAL-40Mhz === DDR-1200Mhz ===
    PLL2 FB_DL: 0xc, 1/0 = 539/485 31000000
    PLL3 FB_DL: 0x16, 1/0 = 754/270 59000000
    PLL4 FB_DL: 0x17, 1/0 = 532/492 5D000000
    do DDR setting..[01F40000]
    Apply DDR3 Setting...(use customer AC)
              0    8   16   24   32   40   48   56   64   72   80   88   96  104  112  120
          --------------------------------------------------------------------------------
    0000:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0001:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0002:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0003:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0004:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0005:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0006:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0007:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0008:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0009:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    000A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    000B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    000C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    000D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    1
    000E:|    0    0    0    0    0    0    0    0    0    1    1    1    1    1    1    1
    000F:|    0    0    0    0    1    1    1    1    1    1    1    1    1    1    0    0
    0010:|    1    1    1    1    1    1    1    1    1    0    0    0    0    0    0    0
    0011:|    1    1    1    1    0    0    0    0    0    0    0    0    0    0    0    0
    0012:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0013:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0014:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0015:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0016:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0017:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0018:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    0019:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001A:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001B:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001C:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001D:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001E:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    001F:|    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
    rank 0 coarse = 15
    rank 0 fine = 72
    B:|    0    0    0    0    0    0    0    0    0    1    1    1    0    0    0    0
    opt_dle value:10
    DRAMC_R0DELDLY[018]=00001E1F
    ==================================================================
                    RX      DQS perbit delay software calibration 
    ==================================================================
    1.0-15 bit dq delay value
    ==================================================================
    bit|     0  1  2  3  4  5  6  7  8  9
    --------------------------------------
    0 |    13 13 15 15 11 12 13 11 9 10 
    10 |    12 11 13 13 11 12 
    --------------------------------------
    
    ==================================================================
    2.dqs window
    x=pass dqs delay value (min~max)center 
    y=0-7bit DQ of every group
    input delay:DQS0 =31 DQS1 = 30
    ==================================================================
    bit     DQS0     bit      DQS1
    0  (1~59)30  8  (1~56)28
    1  (1~57)29  9  (1~55)28
    2  (1~61)31  10  (1~60)30
    3  (1~61)31  11  (0~57)28
    4  (1~60)30  12  (1~60)30
    5  (1~59)30  13  (1~56)28
    6  (1~61)31  14  (1~60)30
    7  (1~60)30  15  (1~57)29
    ==================================================================
    3.dq delay value last
    ==================================================================
    bit|    0  1  2  3  4  5  6  7  8   9
    --------------------------------------
    0 |    14 15 15 15 12 13 13 12 11 12 
    10 |    12 13 13 15 11 13 
    ==================================================================
    ==================================================================
         TX  perbyte calibration 
    ==================================================================
    DQS loop = 15, cmp_err_1 = ffff0000 
    dqs_perbyte_dly.last_dqsdly_pass[0]=15,  finish count=1 
    dqs_perbyte_dly.last_dqsdly_pass[1]=15,  finish count=2 
    DQ loop=15, cmp_err_1 = ffff01ae
    DQ loop=14, cmp_err_1 = ffff0180
    DQ loop=13, cmp_err_1 = ffff0180
    DQ loop=12, cmp_err_1 = ffff0000
    dqs_perbyte_dly.last_dqdly_pass[0]=12,  finish count=1 
    dqs_perbyte_dly.last_dqdly_pass[1]=12,  finish count=2 
    byte:0, (DQS,DQ)=(9,8)
    byte:1, (DQS,DQ)=(9,8)
    20,data:99
    [EMI] DRAMC calibration passed
    
    ===================================================================
                    MT7621   stage1 code done 
                    CPU=500000000 HZ BUS=166666666 HZ
    ===================================================================
    
    
    U-Boot 1.1.3 (Aug  5 2016 - 17:01:25) 0.02
    
    Board: Ralink APSoC DRAM:  128 MB
    relocate_code Pointer at: 87fb8000
    
    Config XHCI 40M PLL 
    ******************************
    Software System Reset Occurred
    ******************************
    flash manufacture id: ef, device id 40 18
    find flash: W25Q128BV
    ============================================ 
    Ralink UBoot Version: 5.0.0.0
    -------------------------------------------- 
    ASIC MT7621A DualCore (MAC to MT7530 Mode)
    DRAM_CONF_FROM: Auto-Detection 
    DRAM_TYPE: DDR3 
    DRAM bus: 16 bit
    Xtal Mode=3 OCP Ratio=1/3
    Flash component: 16 MBytes NOR Flash
    Date:Aug  5 2016  Time:17:01:25
    ============================================ 
    icache: sets:256, ways:4, linesz:32 ,total:32768
    dcache: sets:256, ways:4, linesz:32 ,total:32768 
    
     ##### The CPU freq = 880 MHZ #### 
     estimate memory size =128 Mbytes
    #Reset_MT7530
    set LAN/WAN WLLLL
    
    Please choose the operation: 
       1: Load system code to SDRAM via TFTP. 
       2: Load system code then write to Flash via TFTP. 
       3: Boot system code via Flash (default).
       4: Entr boot command line interface.
       7: Load Boot Loader code then write to Flash via Serial. 
       9: Load Boot Loader code then write to Flash via TFTP. 
                                                                                                                                                                                                                                                         0 
       
    3: System Boot system code via Flash0.
    ## Booting image at bc050000 ...
    
    =================================================
    Check image validation:
    Image1 Trx Check --> 
    ## check_trx, crc=-1234505007, *crc_ret=-1234505007.
    OK
    Image1 Header Magic Number --> OK
    Image1 Header Checksum --> OK
    Image1 Data Checksum --> OK
    
    =================================================
    
    =================================================
    Check image validation:
    Image2 Trx Check --> 
    ## check_trx, crc=-1234505007, *crc_ret=-1234505007.
    OK
    Image2 Header Magic Number --> OK
    Image2 Header Checksum --> OK
    Image2 Data Checksum --> OK
    
    =================================================
    ## check Image1 return 0, check Image2 return 0, Image1 crc=-1234505007, Image2 crc=-1234505007.
    Image1 is ok!
    Image2 is ok and same as Image1!
       Image Name:   MIPS OpenWrt Linux-2.6.36
       Image Type:   MIPS Linux Kernel Image (lzma compressed)
       Data Size:    2639537 Bytes =  2.5 MB
       Load Address: 80001000
       Entry Point:  8000d1d0
       Uncompressing Kernel Image ... OK
    No initrd
    ## Transferring control to Linux (at address 8000d1d0) ...
    ## Giving linux memsize in MB, 128
    
    Starting kernel ...
    
    
    LINUX started...
    
     THIS IS ASIC
    
    SDK 5.0.S.0
    Linux version 2.6.36 (jingwei_liang@sw3-build-01) (gcc version 4.6.3 (Buildroot 2012.11.1) ) #1 SMP Fri Dec 7 12:26:30 CST 2018
    
     The CPU feqenuce set to 880 MHz
    GCMP present
    CPU revision is: 0001992f (MIPS 1004Kc)
    Software DMA cache coherency
    Determined physical RAM map:
     memory: 08000000 @ 00000000 (usable)
    Zone PFN ranges:
      Normal   0x00000000 -> 0x00008000
    Movable zone start PFN for each node
    early_node_map[1] active PFN ranges
        0: 0x00000000 -> 0x00008000
    Detected 3 available secondary CPU(s)
    PERCPU: Embedded 7 pages/cpu @81103000 s6464 r8192 d14016 u65536
    pcpu-alloc: s6464 r8192 d14016 u65536 alloc=16*4096
    pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 32512
    Kernel command line: console=ttyS1,57600n8 root=/dev/mtdblock5 init=/sbin/preinit rootfstype=squashfs,jffs2
    PID hash table entries: 512 (order: -1, 2048 bytes)
    Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
    Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
    Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes.
    Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    Writing ErrCtl register=000492b1
    Readback ErrCtl register=000492b1
    Memory: 122440k/131072k available (3940k kernel code, 8632k reserved, 2433k data, 184k init, 0k highmem)
    Hierarchical RCU implementation.
            Verbose stalled-CPUs detection is disabled.
    NR_IRQS:128
    Trying to install interrupt handler for IRQ24
    Trying to install interrupt handler for IRQ25
    Trying to install interrupt handler for IRQ22
    Trying to install interrupt handler for IRQ9
    Trying to install interrupt handler for IRQ10
    Trying to install interrupt handler for IRQ11
    Trying to install interrupt handler for IRQ12
    Trying to install interrupt handler for IRQ13
    Trying to install interrupt handler for IRQ14
    Trying to install interrupt handler for IRQ16
    Trying to install interrupt handler for IRQ17
    Trying to install interrupt handler for IRQ18
    Trying to install interrupt handler for IRQ19
    Trying to install interrupt handler for IRQ20
    Trying to install interrupt handler for IRQ21
    Trying to install interrupt handler for IRQ23
    Trying to install interrupt handler for IRQ26
    Trying to install interrupt handler for IRQ27
    Trying to install interrupt handler for IRQ28
    Trying to install interrupt handler for IRQ15
    Trying to install interrupt handler for IRQ8
    Trying to install interrupt handler for IRQ29
    Trying to install interrupt handler for IRQ30
    Trying to install interrupt handler for IRQ31
    console [ttyS1] enabled
    Calibrating delay loop... 577.53 BogoMIPS (lpj=1155072)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 512
    launch: starting cpu1
    launch: cpu1 gone!
    CPU revision is: 0001992f (MIPS 1004Kc)
    Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes.
    Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    launch: starting cpu2
    launch: cpu2 gone!
    CPU revision is: 0001992f (MIPS 1004Kc)
    Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes.
    Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    launch: starting cpu3
    launch: cpu3 gone!
    CPU revision is: 0001992f (MIPS 1004Kc)
    Primary instruction cache 32kB, VIPT, , 4-waylinesize 32 bytes.
    Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    Brought up 4 CPUs
    Synchronize counters across 4 CPUs: done.
    NET: Registered protocol family 16
    release PCIe RST: RALINK_RSTCTRL = 7000000
    PCIE PHY initialize
    ***** Xtal 40MHz *****
    start MT7621 PCIe register access
    RALINK_RSTCTRL = 7000000
    RALINK_CLKCFG1 = 77ffeff8
    
    *************** MT7621 PCIe RC mode *************
    PCIE2 no card, disable it(RST&CLK)
    pcie_link status = 0x3
    RALINK_RSTCTRL= 3000000
    *** Configure Device number setting of Virtual PCI-PCI bridge ***
    RALINK_PCI_PCICFG_ADDR = 21007f2 -> 21007f2
    PCIE0 enabled
    PCIE1 enabled
    interrupt enable status: 300000
    Port 1 N_FTS = 1b105000
    Port 0 N_FTS = 1b105000
    config reg done
    init_rt2880pci done
    bio: create slab  at 0
    SCSI subsystem initialized
    pci 0000:00:00.0: BAR 0: can't assign mem (size 0x80000000)
    pci 0000:00:01.0: BAR 0: can't assign mem (size 0x80000000)
    pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
    pci 0000:00:01.0: BAR 8: assigned [mem 0x60100000-0x601fffff]
    pci 0000:00:00.0: BAR 1: assigned [mem 0x60200000-0x6020ffff]
    pci 0000:00:00.0: BAR 1: set to [mem 0x60200000-0x6020ffff] (PCI address [0x60200000-0x6020ffff]
    pci 0000:00:01.0: BAR 1: assigned [mem 0x60210000-0x6021ffff]
    pci 0000:00:01.0: BAR 1: set to [mem 0x60210000-0x6021ffff] (PCI address [0x60210000-0x6021ffff]
    pci 0000:01:00.0: BAR 0: assigned [mem 0x60000000-0x600fffff 64bit]
    pci 0000:01:00.0: BAR 0: set to [mem 0x60000000-0x600fffff 64bit] (PCI address [0x60000000-0x600fffff]
    pci 0000:00:00.0: PCI bridge to [bus 01-01]
    pci 0000:00:00.0:   bridge window [io  disabled]
    pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
    pci 0000:00:00.0:   bridge window [mem pref disabled]
    pci 0000:02:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff 64bit]
    pci 0000:02:00.0: BAR 0: set to [mem 0x60100000-0x601fffff 64bit] (PCI address [0x60100000-0x601fffff]
    pci 0000:00:01.0: PCI bridge to [bus 02-02]
    pci 0000:00:01.0:   bridge window [io  disabled]
    pci 0000:00:01.0:   bridge window [mem 0x60100000-0x601fffff]
    pci 0000:00:01.0:   bridge window [mem pref disabled]
    BAR0 at slot 0 = 0
    bus=0x0, slot = 0x0
    res[0]->start = 0
    res[0]->end = 0
    res[1]->start = 60200000
    res[1]->end = 6020ffff
    res[2]->start = 0
    res[2]->end = 0
    res[3]->start = 0
    res[3]->end = 0
    res[4]->start = 0
    res[4]->end = 0
    res[5]->start = 0
    res[5]->end = 0
    BAR0 at slot 1 = 0
    bus=0x0, slot = 0x1
    res[0]->start = 0
    res[0]->end = 0
    res[1]->start = 60210000
    res[1]->end = 6021ffff
    res[2]->start = 0
    res[2]->end = 0
    res[3]->start = 0
    res[3]->end = 0
    res[4]->start = 0
    res[4]->end = 0
    res[5]->start = 0
    res[5]->end = 0
    bus=0x1, slot = 0x0, irq=0x4
    res[0]->start = 60000000
    res[0]->end = 600fffff
    res[1]->start = 0
    res[1]->end = 0
    res[2]->start = 0
    res[2]->end = 0
    res[3]->start = 0
    res[3]->end = 0
    res[4]->start = 0
    res[4]->end = 0
    res[5]->start = 0
    res[5]->end = 0
    bus=0x2, slot = 0x1, irq=0x18
    res[0]->start = 60100000
    res[0]->end = 601fffff
    res[1]->start = 0
    res[1]->end = 0
    res[2]->start = 0
    res[2]->end = 0
    res[3]->start = 0
    res[3]->end = 0
    res[4]->start = 0
    res[4]->end = 0
    res[5]->start = 0
    res[5]->end = 0
    Switching to clocksource MIPS
    NET: Registered protocol family 2
    IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
    TCP established hash table entries: 4096 (order: 3, 32768 bytes)
    TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
    TCP: Hash tables configured (established 4096 bind 4096)
    TCP reno registered
    UDP hash table entries: 128 (order: 0, 4096 bytes)
    UDP-Lite hash table entries: 128 (order: 0, 4096 bytes)
    NET: Registered protocol family 1
    4 CPUs re-calibrate udelay(lpj = 1167360)
    Load Kernel WDG Timer Module
    Load Ralink Timer0 Module
    Load Ralink Timer2 Module
    squashfs: version 4.0 (2009/01/31) Phillip Lougher
    fuse init (API version 7.15)
    msgmni has been set to 239
    Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
    io scheduler noop registered (default)
    Ralink gpio driver initialized
    @@@@@@#### buffalo_led_init initialized. 
    Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
    serial8250: ttyS0 at MMIO 0x1e000d00 (irq = 27) is a 16550A
    serial8250: ttyS1 at MMIO 0x1e000c00 (irq = 26) is a 16550A
    brd: module loaded
    flash manufacture id: ef, device id 40 18
    W25Q128BV(ef 40180000) (16384 Kbytes)
    mtd .name = raspi, .size = 0x01000000 (16M) .erasesize = 0x00010000 (64K) .numeraseregions = 0
    in find_rootfs_mtd_partitions  off=0x00050000 end=0x00810000
    The  trx header  magic offset 0x00284710
    raspi: squash filesystem found at offset 0x002d4710
    Found image1 partition off 0x002d4710 size 0x0053b8f0
    in find_rootfs_mtd_partitions  off=0x00810000 end=0x00fd0000
    The  trx header  magic offset 0x00284710
    raspi: squash filesystem found at offset 0x00a94710
    Found image2 partition off 0x00a94710 size 0x0053b8f0
    Creating 10 MTD partitions on "raspi":
    0x000000000000-0x000001000000 : "ALL"
    0x000000000000-0x000000030000 : "Bootloader"
    0x000000030000-0x000000040000 : "Config"
    0x000000040000-0x000000050000 : "Factory"
    0x000000050000-0x000000810000 : "Kernel"
    0x0000002d4710-0x000000810000 : "RootFS"
    mtd: partition "RootFS" doesn't start on an erase block boundary -- force read-only
    0x000000810000-0x000000fd0000 : "Kernel2"
    0x000000a94710-0x000000fd0000 : "RootFS2"
    mtd: partition "RootFS2" doesn't start on an erase block boundary -- force read-only
    0x000000fd0000-0x000000fe0000 : "glbcfg"
    0x000000fe0000-0x000000ff0000 : "board_data"
    rdm_major = 253
    GMAC1_MAC_ADRH -- : 0x0000000c
    GMAC1_MAC_ADRL -- : 0x432880ed
    Ralink APSoC Ethernet Driver Initilization. v3.1  1024 rx/tx descriptors allocated, mtu = 1500!
    GMAC1_MAC_ADRH -- : 0x0000000c
    GMAC1_MAC_ADRL -- : 0x43288017
    PROC INIT OK!
    PPP generic driver version 2.4.2
    PPP Deflate Compression module registered
    PPP BSD Compression module registered
    PPP MPPE Compression module registered
    NET: Registered protocol family 24
    IMQ driver loaded successfully.
            Hooking IMQ after NAT on PREROUTING.
            Hooking IMQ before NAT on POSTROUTING.
    register mt_drv
    
    
    === pAd = c0182000, size = 3614952 ===
    
    PciHif.CSRBaseAddress =0xc0080000, csr_addr=0xc0080000!
    RTMPInitPCIeDevice():device_id=0x7615
    DriverOwn()::Try to Clear FW Own...
    DriverOwn()::Success to clear FW Own
    mt_pci_chip_cfg(): HWVer=0x8a10, FWVer=0x8a10, pAd->ChipID=0x7615
    mt_pci_chip_cfg(): HIF_SYS_REV=0x76150001
    RtmpChipOpsHook(492): Not support for HIF_MT yet! MACVersion=0x0
    mt7615_init()-->
    Use 1st iPAiLNA default bin.
    <--mt7615_init()
    ChipOpsMCUHook
    cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
    cut_through_token_list_init(): 87e58308,87e58308
    cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
    cut_through_token_list_init(): 87e58318,87e58318
    ChipID=0x7615
    mt_pci_chip_cfg(): HIF_SYS_REV=0x76150001
    RtmpChipOpsHook(492): Not support for HIF_MT yet! MACVersion=0x0
    mt7615_init()-->
    Use 2nd iPAiLNA default bin.
    <--mt7615_init()
    ChipOpsMCUHook
    cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
    cut_through_token_list_init(): 873e4f88,873e4f88
    cut_through_token_list_init(): TokenList inited done!id_head/tail=0/4096
    cut_through_token_list_init(): 873e4f98,873e4f98
    skb_free start address is 0x87e6269c.
    free_txd: 06b88010, ei_local->cpu_ptr: 06B88000
     POOL  HEAD_PTR | DMA_PTR | CPU_PTR 
    ----------------+---------+--------
         0xa6b88000 0x06B88000 0x06B88000
    
    phy_qrx_ring = 0x06b81000, qrx_ring = 0xa6b81000
    
    phy_rx_ring0 = 0x06b84000, rx_ring0 = 0xa6b84000
    MT7530 Reset Completed!!
    change HW-TRAP to 0x117c8f
    set LAN/WAN WLLLL
    GMAC1_MAC_ADRH -- : 0x000018c2
    GMAC1_MAC_ADRL -- : 0xbf39c5e0
    GDMA2_MAC_ADRH -- : 0x0000000c
    GDMA2_MAC_ADRL -- : 0x43288016
    eth3: ===> VirtualIF_open
    MT7621 GE2 link rate to 1G
    CDMA_CSG_CFG = 81000000
    GDMA1_FWD_CFG = 20710000
    GDMA2_FWD_CFG = 20710000
    Disable flow control
    debug : Enter [BRCTL_ADD_IF] 
    add_if 00000000 ***************************
    device eth2 entered promiscuous mode
    br0: port 1(eth2) entering forwarding state
    br0: port 1(eth2) entering forwarding state
    GDMA2_MAC_ADRH -- : 0x000018c2
    GDMA2_MAC_ADRL -- : 0xbf39c5e0
    eth3: ===> VirtualIF_open
    DriverOwn()::Return since already in Driver Own...
    MacAddress1 = 00:00:00:00:00:00
    MacAddress2 = 00:00:00:00:00:00
    MacAddress3 = 00:00:00:00:00:00
    MacAddress4 = 00:00:00:00:00:00
    E2pAccessMode=2
    RTMPSetProfileParameters(): DBDC Mode=0
    cfg_mode=9
    cfg_mode=9
    wmode_band_equal(): Band Equal!
    APEdca0
    APEdca1
    APEdca2
    APEdca3
    APSDCapable[0]=0
    APSDCapable[1]=0
    APSDCapable[2]=0
    APSDCapable[3]=0
    APSDCapable[4]=0
    APSDCapable[5]=0
    APSDCapable[6]=0
    APSDCapable[7]=0
    APSDCapable[8]=0
    APSDCapable[9]=0
    APSDCapable[10]=0
    APSDCapable[11]=0
    APSDCapable[12]=0
    APSDCapable[13]=0
    APSDCapable[14]=0
    APSDCapable[15]=0
    default ApCliAPSDCapable[0]=0
    default ApCliAPSDCapable[1]=0
    [RTMPSetProfileParameters]Disable DFS/Zero wait=0/0
    AndesSendCmdMsg: Could not send in band command due to diablefRTMP_ADAPTER_MCU_SEND_IN_BAND_CMD
    HT: Ext Channel = ABOVE
    HT: greenap_cap = 0
    IcapMode = 0
    WtcSetMaxStaNum: MaxStaNum:87, BssidNum:5, WdsNum:0, ApcliNum:2, MaxNumChipRept:32, MinMcastWcid:121
    Top Init Done!
    Use dev_alloc_skb
    RX[0] DESC a779e000 size = 8192
    RX[1] DESC a77a0000 size = 8192
    Hif Init Done!
    ctl->txq = c04f2b18
    ctl->rxq = c04f2b24
    ctl->ackq = c04f2b30
    ctl->kickq = c04f2b3c
    ctl->tx_doneq = c04f2b48
    ctl->rx_doneq = c04f2b54
    mt7615_fw_prepare():FW(8a10), HW(8a10), CHIPID(7615))
    mt7615_fw_prepare(2356): MT7615_E3, USE E3 patch and ram code binary image
    AndesMTLoadRomMethodFwDlRing(1035), cap->rom_patch_len(3150)
    AndesRestartCheck: Current TOP_MISC2(0x1)
    AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
    20160419154809a
    
    platform = 
    ALPS
    hw/sw version = 
    8a108a10
    patch version = 
    00000010
    Patch SEM Status=2
    MtCmdPatchSemGet:(ret = 0)
    
    Patch is not ready && get semaphore success, SemStatus(2)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdPatchFinishReq
    EventGenericEventHandler: CMD Success
    Send checksum req..
    Patch SEM Status=3
    MtCmdPatchSemGet:(ret = 0)
    
    Release patch semaphore, SemStatus(3)
    AndesMTEraseRomPatch
    WfMcuHwInit: Before NICLoadFirmware, check IcapMode=0
    AndesMTLoadFwMethodFwDlRing(809), cap->fw_len(452104)
    Build Date:_201803301729
    Build Date:_201803301729
    AndesRestartCheck: Current TOP_MISC2(0x1)
    AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdFwStartReq: override = 1, address = 540672
    EventGenericEventHandler: CMD Success
    Build Date:_201607011611
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdFwStartReq: override = 4, address = 0
    EventGenericEventHandler: CMD Success
    WfMcuHwInit: NICLoadFirmware OK, Check IcapMode=0
    MCU Init Done!
    efuse_probe: efuse = 10000212
    RtmpChipOpsEepromHook::e2p_type=2, inf_Type=5
    RtmpEepromGetDefault::e2p_dafault=1
    RtmpChipOpsEepromHook: E2P type(2), E2pAccessMode = 2, E2P default = 1
    NVM is FLASH mode. dev_idx [0] FLASH OFFSET [0x0]
    ESW: Link Status Changed - Port0 Link UP
    ESW: Link Status Changed - Port3 Link UP
    Country Region from e2p = 101
    mt7615_antenna_default_reset(): TxPath = 4, RxPath = 4
    rtmp_read_txpwr_from_eeprom(224): Don't Support this now!
    RTMPReadTxPwrPerRate(1381): Don't Support this now!
    RcRadioInit(): DbdcMode=0, ConcurrentBand=1
    RcRadioInit(): pRadioCtrl=87640444,Band=0,rfcap=3,channel=1,PhyMode=2
    MtCmdSetDbdcCtrl:(ret = 0)
    Band Rf: 1, Phy Mode: 2
    AntCfgInit(2615): Not support for HIF_MT yet!
    MtSingleSkuLoadParam: RF_LOCKDOWN Feature ON !!!
    MtSingleSkuLoadParam: SKU Table index = 0 
    MtBfBackOffLoadTable: RF_LOCKDOWN Feature ON !!!
    MtBfBackOffLoadTable: BFBackoff Table index = 0 
    EEPROM Init Done!
    mt_mac_init()-->
    mt_mac_pse_init(2715): Don't Support this now!
    mt7615_init_mac_cr()-->
    mt7615_init_mac_cr(): TMAC_TRCR0=0x82783c8c
    mt7615_init_mac_cr(): TMAC_TRCR1=0x82783c8c
    MtAsicSetMacMaxLen(1288): Not finish Yet!
    
    MtCmdSetMacTxRx:(ret = 0)
    mt7615_apply_dcoc() : reload Central CH [1] BW [0] from cetral freq [2417]  offset [2200] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [1] BW [0] from cetral freq [2422] i[44] offset [4b20] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 1,control_ch2=0, central_chl = 1 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [2] BW [0] from cetral freq [2417]  offset [2200] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [2] BW [0] from cetral freq [2422] i[44] offset [4b20] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 2,control_ch2=0, central_chl = 2 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [3] BW [0] from cetral freq [2417]  offset [2200] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [3] BW [0] from cetral freq [2422] i[44] offset [4b20] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 3,control_ch2=0, central_chl = 3 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [4] BW [0] from cetral freq [2432]  offset [2300] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [4] BW [0] from cetral freq [2422] i[44] offset [4b20] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 4,control_ch2=0, central_chl = 4 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    :MtCmdPktBudgetCtrl: bssid(255),wcid(65535),type(0)
    mt7615_apply_dcoc() : reload Central CH [5] BW [0] from cetral freq [2432]  offset [2300] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [5] BW [0] from cetral freq [2442] i[45] offset [4bf8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 5,control_ch2=0, central_chl = 5 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [6] BW [0] from cetral freq [2432]  offset [2300] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [6] BW [0] from cetral freq [2442] i[45] offset [4bf8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 6,control_ch2=0, central_chl = 6 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [7] BW [0] from cetral freq [2447]  offset [2400] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [7] BW [0] from cetral freq [2442] i[45] offset [4bf8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 7,control_ch2=0, central_chl = 7 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [8] BW [0] from cetral freq [2447]  offset [2400] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [8] BW [0] from cetral freq [2442] i[45] offset [4bf8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 8,control_ch2=0, central_chl = 8 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [9] BW [0] from cetral freq [2447]  offset [2400] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [9] BW [0] from cetral freq [2442] i[45] offset [4bf8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 9,control_ch2=0, central_chl = 9 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [10] BW [0] from cetral freq [2467]  offset [2500] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [10] BW [0] from cetral freq [2462] i[46] offset [4cd0] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 10,control_ch2=0, central_chl = 10 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [11] BW [0] from cetral freq [2467]  offset [2500] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [11] BW [0] from cetral freq [2462] i[46] offset [4cd0] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 11,control_ch2=0, central_chl = 11 DBDCIdx= 0, Band= 0 
    BW = 0,TXStream = 4, RXStream = 4, scan(1)
    ====================================================================
    Channel   1 : Busy Time =   2021, Skip Channel = FALSE, BwCap = TRUE
    Channel   2 : Busy Time =   2492, Skip Channel = FALSE, BwCap = TRUE
    Channel   3 : Busy Time =   2300, Skip Channel = FALSE, BwCap = TRUE
    Channel   4 : Busy Time =   1833, Skip Channel = FALSE, BwCap = TRUE
    Channel   5 : Busy Time =   1394, Skip Channel = FALSE, BwCap = TRUE
    Channel   6 : Busy Time =  10251, Skip Channel = FALSE, BwCap = TRUE
    Channel   7 : Busy Time =  12595, Skip Channel = FALSE, BwCap = TRUE
    Channel   8 : Busy Time =  10846, Skip Channel = FALSE, BwCap = TRUE
    Channel   9 : Busy Time =   9892, Skip Channel = FALSE, BwCap = TRUE
    Channel  10 : Busy Time =  10472, Skip Channel = FALSE, BwCap = TRUE
    Channel  11 : Busy Time =   2445, Skip Channel = FALSE, BwCap = TRUE
    ====================================================================
    Rule 3 Channel Busy time value : Select Primary Channel 5 
    Rule 3 Channel Busy time value : Min Channel Busy = 1394
    Rule 3 Channel Busy time value : BW = 20
    ApAutoChannelAtBootUprxq = c0972b24
    ctl->ackq = c0972b30
    ctl->kickq = c0972b3c
    ctl->tx_doneq = c0972b48
    ctl->rx_doneq = c0972b54
    mt7615_fw_prepare():FW(8a10), HW(8a10), CHIPID(7615))
    mt7615_fw_prepare(2356): MT7615_E3, USE E3 patch and ram code binary image
    AndesMTLoadRomMethodFwDlRing(1035), cap->rom_patch_len(3150)
    AndesRestartCheck: Current TOP_MISC2(0x1)
    AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
    20160419154809a
    
    platform = 
    ALPS
    hw/sw version = 
    8a108a10
    patch version = 
    00000010
    Patch SEM Status=2
    MtCmdPatchSemGet:(ret = 0)
    
    Patch is not ready && get semaphore success, SemStatus(2)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdPatchFinishReq
    EventGenericEventHandler: CMD Success
    Send checksum req..
    Patch SEM Status=3
    MtCmdPatchSemGet:(ret = 0)
    
    Release patch semaphore, SemStatus(3)
    AndesMTEraseRomPatch
    WfMcuHwInit: Before NICLoadFirmware, check IcapMode=0
    AndesMTLoadFwMethodFwDlRing(809), cap->fw_len(452104)
    Build Date:_201803301729
    Build Date:_201803301729
    AndesRestartCheck: Current TOP_MISC2(0x1)
    AndesRestartCheck: (TOP_MISC2 = 1), ready to continue...RET(0)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdFwStartReq: override = 1, address = 540672
    EventGenericEventHandler: CMD Success
    Build Date:_201607011611
    EventGenericEventHandler: CMD Success
    MtCmdAddressLenReq:(ret = 0)
    MtCmdFwStartReq: override = 4, address = 0
    EventGenericEventHandler: CMD Success
    WfMcuHwInit: NICLoadFirmware OK, Check IcapMode=0
    MCU Init Done!
    efuse_probe: efuse = 10000212
    RtmpChipOpsEepromHook::e2p_type=2, inf_Type=5
    RtmpEepromGetDefault::e2p_dafault=1
    RtmpChipOpsEepromHook: E2P type(2), E2pAccessMode = 2, E2P default = 1
    NVM is FLASH mode. dev_idx [1] FLASH OFFSET [0x8000]
    Country Region from e2p = 101
    mt7615_antenna_default_reset(): TxPath = 4, RxPath = 4
    rtmp_read_txpwr_from_eeprom(224): Don't Support this now!
    RTMPReadTxPwrPerRate(1381): Don't Support this now!
    RcRadioInit(): DbdcMode=0, ConcurrentBand=1
    RcRadioInit(): pRadioCtrl=873e1444,Band=0,rfcap=3,channel=1,PhyMode=2
    MtCmdSetDbdcCtrl:(ret = 0)
    Band Rf: 1, Phy Mode: 2
    AntCfgInit(2615): Not support for HIF_MT yet!
    MtSingleSkuLoadParam: RF_LOCKDOWN Feature ON !!!
    MtSingleSkuLoadParam: SKU Table index = 0 
    MtBfBackOffLoadTable: RF_LOCKDOWN Feature ON !!!
    MtBfBackOffLoadTable: BFBackoff Table index = 0 
    EEPROM Init Done!
    mt_mac_init()-->
    mt_mac_pse_init(2715): Don't Support this now!
    mt7615_init_mac_cr()-->
    mt7615_init_mac_cr(): TMAC_TRCR0=0x82783c8c
    mt7615_init_mac_cr(): TMAC_TRCR1=0x82783c8c
    MtAsicSetMacMaxLen(1288): Not finish Yet!
    
    MtCmdSetMacTxRx:(ret = 0)
    mt7615_apply_dcoc() : reload Central CH [42] BW [2] from cetral freq [5210]  offset [1900] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [42] BW [2] from cetral freq [5220] i[9] offset [2d98] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 36,control_ch2=0, central_chl = 42 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [42] BW [2] from cetral freq [5210]  offset [1900] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [42] BW [2] from cetral freq [5220] i[9] offset [2d98] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 40,control_ch2=0, central_chl = 42 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [42] BW [2] from cetral freq [5210]  offset [1900] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [42] BW [2] from cetral freq [5220] i[9] offset [2d98] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 44,control_ch2=0, central_chl = 42 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [42] BW [2] from cetral freq [5210]  offset [1900] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [42] BW [2] from cetral freq [5220] i[9] offset [2d98] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 48,control_ch2=0, central_chl = 42 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    :MtCmdPktBudgetCtrl: bssid(255),wcid(65535),type(0)
    mt7615_apply_dcoc() : reload Central CH [58] BW [2] from cetral freq [5290]  offset [1a00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [58] BW [2] from cetral freq [5300] i[13] offset [30f8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 52,control_ch2=0, central_chl = 58 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [58] BW [2] from cetral freq [5290]  offset [1a00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [58] BW [2] from cetral freq [5300] i[13] offset [30f8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 56,control_ch2=0, central_chl = 58 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [58] BW [2] from cetral freq [5290]  offset [1a00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [58] BW [2] from cetral freq [5300] i[13] offset [30f8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 60,control_ch2=0, central_chl = 58 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [58] BW [2] from cetral freq [5290]  offset [1a00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [58] BW [2] from cetral freq [5300] i[13] offset [30f8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 64,control_ch2=0, central_chl = 58 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [106] BW [2] from cetral freq [5530]  offset [1d00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [106] BW [2] from cetral freq [5540] i[25] offset [3b18] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 100,control_ch2=0, central_chl = 106 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [106] BW [2] from cetral freq [5530]  offset [1d00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [106] BW [2] from cetral freq [5540] i[25] offset [3b18] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 104,control_ch2=0, central_chl = 106 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [106] BW [2] from cetral freq [5530]  offset [1d00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [106] BW [2] from cetral freq [5540] i[25] offset [3b18] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 108,control_ch2=0, central_chl = 106 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [106] BW [2] from cetral freq [5530]  offset [1d00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [106] BW [2] from cetral freq [5540] i[25] offset [3b18] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 112,control_ch2=0, central_chl = 106 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [122] BW [2] from cetral freq [5610]  offset [1e00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [122] BW [2] from cetral freq [5620] i[29] offset [3e78] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 116,control_ch2=0, central_chl = 122 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [122] BW [2] from cetral freq [5610]  offset [1e00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [122] BW [2] from cetral freq [5620] i[29] offset [3e78] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 120,control_ch2=0, central_chl = 122 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [122] BW [2] from cetral freq [5610]  offset [1e00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [122] BW [2] from cetral freq [5620] i[29] offset [3e78] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 124,control_ch2=0, central_chl = 122 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    mt7615_apply_dcoc() : reload Central CH [122] BW [2] from cetral freq [5610]  offset [1e00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [122] BW [2] from cetral freq [5620] i[29] offset [3e78] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 128,control_ch2=0, central_chl = 122 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(1)
    ====================================================================
    Channel  36 : Busy Time =   1087, Skip Channel = FALSE, BwCap = TRUE
    Channel  40 : Busy Time =   2110, Skip Channel = FALSE, BwCap = TRUE
    Channel  44 : Busy Time =    599, Skip Channel = FALSE, BwCap = TRUE
    Channel  48 : Busy Time =   1352, Skip Channel = FALSE, BwCap = TRUE
    Channel  52 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel  56 : Busy Time =    187, Skip Channel = FALSE, BwCap = TRUE
    Channel  60 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel  64 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 100 : Busy Time =    219, Skip Channel = FALSE, BwCap = TRUE
    Channel 104 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 108 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 112 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 116 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 120 : Busy Time =    484, Skip Channel = FALSE, BwCap = TRUE
    Channel 124 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    Channel 128 : Busy Time =      0, Skip Channel = FALSE, BwCap = TRUE
    ====================================================================
    Rule 3 Channel Busy time value : Select Primary Channel 52 
    Rule 3 Channel Busy time value : Min Channel Busy = 187
    Rule 3 Channel Busy time value : BW = 80
    ApAutoChannelAtBootUp<-----------------
    MtAsicSetChBusyStat(840): Not support for HIF_MT yet!
    HcUpdatePhyMode(): Update PhyMode for all wdev for this band PhyMode:49,Channel=52
    CountryCode(2.4G/5G)=1/1, RFIC=25, PHY mode(2.4G/5G)=49/49, support 19 channels
    wtc_acquire_groupkey_wcid: Found a non-occupied wtbl_idx:127 for WDEV_TYPE:1
     LinkToOmacIdx = 0, LinkToWdevType = 1
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 8196,                 CmdBssInfoBmcRate.u2McTransmit = 8196
    LeadTimeForBcn, OmacIdx = 0, WDEV_WITH_BCN_ABILITY
    [RadarStateCheck]Set into RD_SILENCE_MODE! 
    MtCmdTxPowerSKUCtrl: fgTxPowerSKUEn = 0
    MtCmdTxPowerPercentCtrl: fgTxPowerPercentEn = 0
    MtCmdTxBfBackoffCtrl: fgTxBFBackoffEn = 0
    mt7615_bbp_adjust():rf_bw=2, ext_ch=1, PrimCh=52, HT-CentCh=54, VHT-CentCh=58
    mt7615_apply_dcoc() : reload Central CH [58] BW [2] from cetral freq [5290]  offset [1a00] 
    MtCmdGetRXDCOCCalResult:(ret = 0)
    mt7615_apply_dpd() : reload Central CH [58] BW [2] from cetral freq [5300] i[13] offset [30f8] 
    MtCmdGetTXDPDCalResult:(ret = 0)
    MtCmdChannelSwitch: control_chl = 52,control_ch2=0, central_chl = 58 DBDCIdx= 0, Band= 0 
    BW = 2,TXStream = 4, RXStream = 4, scan(0)
    ap_phy_rrm_init_byRf(): AP Set CentralFreq at 58(Prim=52, HT-CentCh=54, VHT-CentCh=58, BBP_BW=2)
    [WrapDfsRadarDetectStart]: Band0Ch is 52[WrapDfsRadarDetectStart]: Band1Ch is 0MtAsicSetRalinkBurstMode(2594): Not support for HIF_MT yet!
    MtAsicSetPiggyBack(777): Not support for HIF_MT yet!
    MtAsicSetTxPreamble(2573): Not support for HIF_MT yet!
    Main bssid = 18:c2:bf:39:c5:e4
    AsicRadioOnOffCtrl(): DbdcIdx=0 RadioOn
    MtCmdSetMacTxRx:(ret = 0)
    MCS Set = ff ff ff ff 01
    MtCmdSetMacTxRx:(ret = 0)
    <==== mt_wifi_init, Status=0
    MtCmdEDCCACtrl: BandIdx: 0, EDCCACtrl: 1 
    MtCmdEDCCACtrl: BandIdx: 1, EDCCACtrl: 1 
    WtcSetMaxStaNum: MaxStaNum:87, BssidNum:5, WdsNum:0, ApcliNum:2, MaxNumChipRept:32, MinMcastWcid:121
    red_is_enabled: set CR4/N9 RED Enable to 1.
    cp_support_is_enabled: set CR4 CP_SUPPORT to Mode 2.
    Generate UUID for apidx(0)
    UUID: c063412c, len = 16
    0x0000 : bc 32 9e 00 1d d8 11 b2 86 01 18 c2 bf 39 c5 e1 
    
    debug : Enter [BRCTL_ADD_RULE_IF] 
    add_if 00000100 ***************************
    device rai0 entered promiscuous mode
    br0: port 3(rai0) entering forwarding state
    br0: port 3(rai0) entering forwarding state
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 0,                 CmdBssInfoBmcRate.u2McTransmit = 0
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 8196,                 CmdBssInfoBmcRate.u2McTransmit = 8196
    bssUpdateBmcMngRate (BSS_INFO_BROADCAST_INFO),                 CmdBssInfoBmcRate.u2BcTransmit= 8192,                 CmdBssInfoBmcRate.u2McTransmit = 8192
    Jan  1 00:00:31 miniupnpd[488]: WPS listening on port 53210
    mcsnoop: module license 'BUFFALO Inc. PROPRIETARY' taints kernel.
    Disabling lock debugging due to kernel taint
    mcsnoop: flush all snoop entry
    mcsnoop: Bridge Multicast Snooping module Ver0.1/20070912
    mcsnoop_br_ioctl_device:275: mcast_maxage 75000 / 250
    device eth2 left promiscuous mode
    br0: port 1(eth2) entering forwarding state
    debug : Enter [BRCTL_ADD_RULE_IF] 
    add_if 00000600 ***************************
    device eth2 entered promiscuous mode
    br0: port 1(eth2) entering forwarding state
    br0: port 1(eth2) entering forwarding state
    netwatchd uses obsolete (PF_INET,SOCK_PACKET)
    Jan  1 00:00:32 crond[555]: crond: crond (busybox 1.18.5) started, log level 8
    [WrapDfsRddReportHandle]:  Radar detected !!!!!!!!!!!!!!!!!
    MtAsicSetPiggyBack(777): Not support for HIF_MT yet!
    ExtEventBeaconLostHandler::FW LOG, Beacon lost (18:c2:bf:39:c5:e4), Reason 0x10
      Beacon lost - AP disabled!!!
    WifiSysGetBssInfoState(): BssInfoIdx 0 not found!!!
    WifiSysUpdateBssInfoState(): BssInfoIdx 0 not found!!!
    MtAsicSetRalinkBurstMode(2594): Not support for HIF_MT yet!
    MtAsicSetPiggyBack(777): Not support for HIF_MT yet!
    ntp.jst.mfeed.adMtAsicSetTxPreamble(2573): Not support for HIF_MT yet!
    .jp: Unknown hoswdev_attr_update(): wdevId0 = 18:c2:bf:39:c5:e4
    t
    MtCmdSetDbdcCtrl:(ret = 0)
    HcUpdatePhyMode(): Update PhyMode for all wdev for this band PhyMode:49,Channel=104
    Link Status Changed - WAN Port Link UP